In recent years, with the spread of portable telephones, mobile communication systems utilizing analog or digital modulation have been extensively developed. Since portable telephones use batteries as power sources, reduction of power consumption is very important for long-time operation. In a portable telephone, a power amplifier amplifies a signal amplitude to an antenna output, and the power consumption of the power amplifier amounts to 70-80% of the total power consumption of the portable telephone. Therefore, it is very important for the reduction in the power consumption to increase the efficiency of the power amplifier.
FIG. 13 is a block diagram illustrating a structure of a transmitter of an ordinary analog modulation (frequency modulation) type portable telephone. In the figure, a control circuit 1 controls a voltage-controlled crystal oscillator 2 (hereinafter referred to as a VCXO) in response to speech signal data (hereinafter referred to as IN-data). The VCXO 2 performs frequency modulation in response to the IN-data and outputs a frequency modulated signal (hereinafter referred to as FM signal) in the intermediate frequency band (hereinafter referred to as IF band) to a mixer 3. A frequency synthesizer 4 produces a carrier wave signal in the radio frequency band (hereinafter referred to as RF band) and outputs the signal to the mixer 3. The mixer 3 mixes the FM signal in the IF band with the carrier wave signal in the RF band to convert the FM signal in the IF band into an FM signal in the RF band. A band-pass filter (hereinafter referred to as BPF) 5 eliminates unnecessary waves caused by the frequency conversion from the FM signal in the RF band. A power amplifier 6 amplifies the power level of the FM signal in the RF band to a power level of an antenna output. A BPF 7 eliminates unnecessary waves caused by the amplification from the FM signal and transmits a signal in a frequency band suitable for transmission. The signal transmitted through the BPF 7 is radiated into space from an antenna 9. On the other hand, signals received by the antenna 9 are applied to a BPF 8. The BPF 8 transmits only a signal in a frequency band to be received by a receiving circuit 10. The BPF 8 and the receiving circuit 10 are constituents of a receiver.
FIG. 14 is a block diagram illustrating the power amplifier 6 in more detail. An input terminal IN of the power amplifier 6 is connected through an input matching circuit M1 to an input end of a driver stage A1 for driving an output amplifier stage A2. An output end of the driver stage A1 is connected through an inter-stage matching circuit M12 and an AC coupling capacitor C1 to an input end of the output amplifier stage A2. An output end of the output amplifier stage A2 is connected through an output matching circuit M2 to an output terminal OUT. The driver stage A1 comprises an FET having a gate bias terminal Vg1 and a drain bias terminal Vd1, and the output amplifier stage A2 comprises an FET having a gate bias terminal Vg2 and a drain bias terminal Vd2.
Generally, in transmitters of portable telephones, an output power exceeding 1 W is required for the analog modulation (frequency modulation). In order to improve the efficiency in the high-power output operation exceeding 1 W, various means, such as harmonic processing techniques, have been adopted in the design of the power amplifier. However, the transmitter of the portable telephone operates at a high power level near the maximum power level when it is used in a place far from the base station. On the other hand, when the transmitter is used in a place near the base station, it is preferable that the transmitter should be used at a low power level, for example, 10-20 dB reduced per 1 W, to increase the lifetime of the battery. That is, it is desired to reduce the current consumption of the power amplifier of the transmitter. In order to realize the low-power output operation of the transmitter, in the prior art power amplifier 6 shown in FIG. 14, bias voltages applied to the gate bias terminals Vg1 and Vg2 and the drain bias terminals Vd1 and Vd2 of the driver stage A1 and the output amplifier stage A2 are controlled to reduce the current consumption of the output amplifier stage A2 which consumes most of the power in the low-power output operation. Although the input power applied to the input terminal IN of the power amplifier 6 is usually constant, the input power may be controlled to realize the low-power output operation of the power amplifier 6.
FIG. 15 is a graph illustrating a relationship between the output power and the current consumption when the gate bias voltages applied to the gate bias terminals Vg1 and Vg2 and the drain bias voltages applied to the drain bias terminals Vd1 and Vd2 are controlled in the prior art power amplifier 6. In the graph, a point A denotes the current consumption when the output power is 1 W, a point B denotes the current consumption when the output power is 100 mW (1 W-10 dB), and a point C denotes the current consumption when the output power is 10mW (1 W-20 dB).
FIG. 16 is a graph illustrating the input power vs. output power characteristics and the input power vs. power added efficiency characteristics of the power amplifier 6. In the graph, continuous lines X1 and X2 show the input power vs. output power characteristics in the high-power output operation and the low-power output operation of the power amplifier 6, respectively, and dotted lines Y1 and Y2 show the input power vs. power added efficiency characteristics in the high-power output operation and the low-power output operation of the power amplifier 6, respectively. Further, points a1 and a2 show the output power and the power added efficiency at the point A of FIG. 15, respectively, and points c1 and c2 show the output power and the power added efficiency at the point C of FIG. 15, respectively. The input power to a1, a2, c1, and c2 is fixed at a prescribed value .DELTA..
As shown in FIG. 16, in the prior art power amplifier, a high-efficiency operation with the power added efficiency of 50-60% is realized by a higher harmonic processing circuit or the like included in the matching circuit M2 during the high-power output operation (point A in FIG. 15). However, in the low-power output operation (point C in FIG. 15), the efficiency is significantly reduced to several percent. The reason for the reduction in the efficiency is described hereinafter. Even when the drain bias voltage is reduced to reduce the current consumption by the power amplifier 6, since the voltage supplied from the battery is fundamentally constant, the power consumption with respect to DC and viewed from the battery side depends on the reduction in the current only. In addition, since the gate width of the FET of the output amplifier stage A2 is increased to improve the efficiency in the high-power output operation, the control of the drain bias voltage alone is not enough for a significant reduction in the current consumption. For example, when the drain voltage is reduced while maintaining the operation of the FET, the current consumption exceeds 100 mA.
As described above, a1though the prior art power amplifier 6 operates efficiently during the high-power, a1most the maximum power, output operation, the efficiency is significantly reduced during the low-power output operation.
In order to solve the above-described problem, Japanese Published Patent Application No. Hei. 3-104408 discloses a power amplifier in which a plurality of amplifier circuits providing different amplified outputs are connected in parallel between an input terminal and an output terminal and voltages applied to the amplifier circuits are controlled. FIG. 17 is a block diagram illustrating the power amplifier. The power amplifier comprises three amplifier circuits connected in parallel with each other between an input terminal IN and an output terminal OUT. A first amplifier circuit comprises an amplifier FET 11a, an input side matching circuit 12a, and an output side matching circuit 13a. A second amplifier circuit comprises an amplifier FET 11b, an input side matching circuit 12b, and an output side matching circuit 13b. A third amplifier circuit comprises an amplifier FET 11c, an input side matching circuit 12c, and an output side matching circuit 13c. A control circuit 16 is connected between a power supply 15 and gate electrodes of the respective FETs 11a to 11c and controls voltages applied to the gate electrodes of the FETs. A power supply 14 is connected to drain electrodes of the respective FETs 11a to 11c.
In this prior art power amplifier, the amplifier FETs 11a to 11c are selectively driven by the control circuit 16, whereby the power level of the amplified output applied to the output terminal OUT is changed. In addition, these amplifier FETs are designed so as to operate efficiently. Therefore, a plurality of amplified outputs with different power levels are obtained.
In this prior art power amplifier, however, the matching circuits 13a and 13b on the output side of the amplifier FETs 11a to 11c are directly connected to the output terminal OUT as shown in FIG. 17. In this case, when the amplifier FET 11a is driven while the amplifier FETs 11b and 11c are not driven, not only the matching circuit 13a for the amplifier FET 11a that outputs amplified signals but a1so the matching circuits 13b and 13c for the amplifier FETs 11b and 11c that do not output amplified signals are electrically connected to the output terminal OUT. Therefore, in order to selectively operate those three amplifier FETs efficiently, the impedance of the output side matching circuit for the operated, i.e., selected, amplifier FET has to be controlled so as to have an optimum load curve along which the amplifier FET operates efficiently, while considering the impedances of the unselected amplifier FETs and the output side matching circuits therefor. However, it is very difficult to set the impedance of the output side matching circuit for the selected amplifier FET while considering the impedances of the output side matching circuits for the unselected amplifier FETs because the impedance of one matching circuit varies with a variation in the impedance of the other matching circuit. Actually, it is difficult to selectively operate the amplifier FETs providing different amplified outputs with high efficiency. Furthermore, since the amplifier circuit in which the amplifier FET is operated is electrically connected to the amplifier circuit in which the amplifier FET is not operated, a feedback loop is produced between these amplifier circuits, resulting in an incidental oscillation.